256Mb: x16, x32 2.5V VEXT, 1.8V VDD, 1.8V VDDQ, RLDRAM
Features
REDUCED LATENCY DRAM (RLDRAM®)
MT49H8M32 – 1 Meg x 32 x 8 banks
MT49H16M16 – 2 Meg x 16 x 8 banks
For the latest data sheet, refer to Micron’s Web site: www.micron.com/rldram
Features
Figure 1:
• Organization 8 Meg x 32, 16 Meg x 16 in 8 banks
• Cyclic bank addressing for maximum data
bandwidth
• Non multiplexed addresses
• Non interruptible sequential burst of two (2-bit
prefetch) and four (4-bit prefetch) DDR
• Up to 600 Mb/sec/pin data rate
• Programmable READ latency (RL) of 5-6
• Data valid signal (DVLD) activated as read data is
available
• Data mask signals (DM0/DM1) to mask first and
• second part of write data burst
• IEEE 1149.1 compliant JTAG boundary scan
• 2.5V VEXT, 1.8V VDD, 1.8V VDDQ I/O
• Pseudo-HSTL 1.8V I/O Supply
• Internal auto precharge
• Refresh requirements: 32ms at 95°C case
temperature (8K refresh for each bank, 64K refresh
command must be issued in total each 32ms)
• 144-pin, 11mm x 18.5mm µBGA package
Options
Table 1:
Valid Part Numbers
Part Number
Description
MT49H8M32FM-xx
MT49H16M16FM-xx
8 Meg x 32
16 Meg x 16
General Description
The Micron® 256Mb reduced latency DRAM
(RLDRAM®) contains 8 banks x32Mb of memory
accessible with 32-bit or 16-bit I/Os in a double data
rate (DDR) form at where the data is provided and synchronized with a differential echo clock signal.
RLDRAM does not require row/column address multiplexing and is optimized for fast random access and
high-speed bandwidth.
Marking
• Clock Cycle Timing
3.3ns (300 MHz)
4ns (250 MHz)
5ns (200 MHz)
• Configuration
8 Meg x 32 (1 Meg x 32 x 8 banks)
16 Meg x 16 (2 Meg x 16 x 8 banks)
• Operating temperature range
Commercial: 0° to +95°C
Industrial: TC = -40°C to +95°C
TA = -40°C to 85°C)
• Package
144-ball, 11mm x 18.5mm
µBGA (Standard)
144-ball, 11mm x 18.5mm
µBGA (Lead-Free)
144-Ball µBGA
-33
-4
-5
MT49H8M32
MT49H16M16
RLDRAM is designed for high bandwidth communication data storage—telecommunications, networking,
and cache applications, etc.
None
IT
FM
BM1
Notes: 1. Contact factory for availability.
pdf: 09005aef81121545/source: 09005aef810c0ffc
256Mbx16x32RLDRAM_1.fm - Rev F 8/05 EN
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
256Mb: x16, x32 2.5V VEXT, 1.8V VDD, 1.8V VDDQ, RLDRAM
Table of Contents
Table of Contents
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Functional Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Ball Assignment and Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Mode Register Set Command (MRS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Configuration Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Write Basic Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Read Basic Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
AUTO REFRESH Command (AREF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
IEEE 1149.1 Serial Boundary Scan (JTAG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Disabling The JTAG Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Test Access Port (TAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Test Clock (TCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Test Mode Select (TMS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Test Data-in (TDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Test Data-out (TDO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Performing A Tap RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Tap Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Instruction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Bypass Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Boundary Scan Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Identification (Id) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Tap Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
EXTEST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
IDCODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
SAMPLE/PRELOAD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
BYPASS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Reserved for Future Use . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Recommended DC Operation Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
pdf: 09005aef81121545/source: 09005aef810c0ffc
256M_16_32_RLDRAM1TOC.fm - Rev F 8/05 EN
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001 Micron Technology, Inc. All rights reserved.
256Mb: x16, x32 2.5V VEXT, 1.8V VDD, 1.8V VDDQ, RLDRAM
List of Figures
List of Figures
Figure 1:
Figure 2:
Figure 3:
Figure 4:
Figure 5:
Figure 6:
Figure 7:
Figure 8:
Figure 9:
Figure 10:
Figure 11:
Figure 12:
Figure 13:
Figure 14:
Figure 15:
Figure 16:
Figure 17:
Figure 18:
Figure 19:
Figure 20:
Figure 21:
Figure 22:
Figure 23:
Figure 24:
Figure 25:
Figure 26:
Figure 27:
Figure 28:
Figure 29:
Figure 30:
Figure 31:
Figure 32:
144-Ball µBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
8 Meg x 32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
16 Meg x 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Clock Command/Address Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Power-Up Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Clock Input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Mode Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Mode Register Set Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Mode Register Bit Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
WRITE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Basic WRITE Burst Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
WRITE Burst Basic Sequence: BL = 2; WL = 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
WRITE Burst Basic Sequence: BL = 4; WL = 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
WRITE Data Mask Timing: BL = 2; WL = 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Write Data Mask Timing: BL = 4; WL = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
WRITE followed by READ: BL = 4; RL = 5; WL = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
READ Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Basic READ Burst Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
READ Burst: BL = 2; RL = 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
READ Burst: BL = 4; RL = 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
READ followed by WRITE: BL = 2; RL = 5; WL = 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
READ followed by WRITE: BL = 2; RL = 5; WL = 2 – Interleaved Data . . . . . . . . . . . . . . . . . . . . . . . . . . .24
READ followed by WRITE: BL = 4; RL = 5; WL = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
READ followed by WRITE: BL = 4; RL = 5; WL = 1 – Interleaved Data . . . . . . . . . . . . . . . . . . . . . . . . . . .25
AUTO REFRESH Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
AUTO REFRESH Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
TAP Controller State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
TAP Controller Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
TAP Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Output Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
144-Ball µBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
pdf: 09005aef81121545/source: 09005aef810c0ffc
256M_16_32_RLDRAM1LOF.fm - Rev F 8/05 EN
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001 Micron Technology, Inc. All rights reserved.
256Mb: x16, x32 2.5V VEXT, 1.8V VDD, 1.8V VDDQ, RLDRAM
List of Tables
List of Tables
Table 1:
Table 2:
Table 3:
Table 4:
Table 5:
Table 6:
Table 7:
Table 8:
Table 9:
Table 10:
Table 12:
Table 14:
Table 15:
Table 16:
Table 17:
Table 18:
Table 19:
Table 20:
Table 21:
Table 22:
Table 23:
Valid Part Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
8 Meg x 32 Ball Assignment (Top View) 144-Ball µBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
16 Meg x 16 Ball Assignment (Top View) 144-Ball µBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Ball Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Address Widths at Different Burst Lengths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Command Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Description of Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Clock Input Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
RLDRAM Configuration Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
TAP DC Electrical Characteristics and Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Identification Register Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Scan Register Sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Instruction Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Boundary Scan (Exit) Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
DC Electrical Characteristics and Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
DC Electrical Characteristics and Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
AC Electrical Characteristics and Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
IDD Operating Conditions and Maximum Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
pdf: 09005aef81121545/source: 09005aef810c0ffc
256M_16_32_RLDRAM1LOT.fm - Rev F 8/05 EN
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001 Micron Technology, Inc. All rights reserved.
256Mb: x16, x32 2.5V VEXT, 1.8V VDD, 1.8V VDDQ, RLDRAM
Functional Block Diagrams
Functional Block Diagrams
Figure 2:
8 Meg x 32
Note:
pdf: 09005aef81121545/source: 09005aef810c0ffc
256Mbx16x32RLDRAM_2.fm - Rev F 8/05 EN
Output Buffers
DQ0–DQ31
Sense Amp and Data Bus
Column Decoder
Column Decoder
Sense Amp and Data Bus
Bank 7
Control Logic and Timing Generator
VREF
Input Buffers
Bank 6
Memory Array
DM1
DQS[3:0], DQS#[3:0]
Bank 5
Memory Array
DM0
DVLD
Bank 3
Row Decoder
CS#
Data Read Strobe
Bank 2
Memory Array
REF#
Data Valid
Memory Array
Column Decoder
Bank 4
Column Decoder
Memory Array
Memory Array
Row Decoder
Sense Amp and Data Bus
Row Decoder
Sense Amp and Data Bus
Column Decoder
Sense Amp and Data Bus
Row Decoder
Bank 1
Row Decoder
AS#
Bank 0
Memory Array
Column Decoder
Column Decoder
Memory Array
Row Decoder
WE#
Row Decoder
Refresh
Counter
CK
Row Decoder
Row Address
Buffer
C?K#
Column Address
Buffer
Sense Amp and Data Bus
Column Address
Counter
Sense Amp and Data Bus
Column Decoder
Sense Amp and Data Bus
A0–A18, B0, B1, B2
When the BL = 4 setting is used, A18 is a “Don’t Care.“
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001 Micron Technology, Inc. All rights reserved.
256Mb: x16, x32 2.5V VEXT, 1.8V VDD, 1.8V VDDQ, RLDRAM
Functional Block Diagrams
Figure 3:
16 Meg x 16
Output Buffers
DQ0–DQ15
Sense Amp and Data Bus
Column Decoder
Column Decoder
Sense Amp and Data Bus
Bank 7
Control Logic and Timing Generator
VREF
Input Buffers
Bank 6
Memory Array
DM1
DQS[1:0], DQS#[1:0]
Bank 5
Memory Array
DM0
DVLD
Bank 3
Row Decoder
CS#
Data Read Strobe
Bank 2
Memory Array
REF#
Data Valid
Memory Array
Column Decoder
Bank 4
Column Decoder
Memory Array
Memory Array
Row Decoder
Sense Amp and Data Bus
Row Decoder
Sense Amp and Data Bus
Column Decoder
Sense Amp and Data Bus
Row Decoder
Bank 1
Row Decoder
AS#
Bank 0
Memory Array
Column Decoder
Column Decoder
Memory Array
Row Decoder
WE#
Row Decoder
Refresh
Counter
CK
Row Decoder
Row Address
Buffer
CK#
Column Address
Buffer
Sense Amp and Data Bus
Column Address
Counter
Sense Amp and Data Bus
Column Decoder
Sense Amp and Data Bus
A0–A19, B0, B1, B2
Notes: 1. When the BL = 4 setting is used, A19 is a “Don’t Care.”
2. In the 16 Meg x 16 configuration, only DQS[1:0] and DQS#[1:0] are used.
pdf: 09005aef81121545/source: 09005aef810c0ffc
256Mbx16x32RLDRAM_2.fm - Rev F 8/05 EN
6
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001 Micron Technology, Inc. All rights reserved.
256Mb: x16, x32 2.5V VEXT, 1.8V VDD, 1.8V VDDQ, RLDRAM
Ball Assignment and Description
Ball Assignment and Description
Table 2:
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
8 Meg x 32 Ball Assignment (Top View) 144-Ball µBGA
1
VSS
VSS
VSS
VSS
VSS
DM0
A5
A8
AS#
WE#
A18
A15
DM1
VSS
VSS
VSS
VSS
VSS
2
3
VEXT
DQ8
DQ10
DQS1
DQ12
DQ14
A6
A9
B2
REF#
CS#
A16
DQ22
DQ20
DQS2
DQ18
DQ16
VEXT
VREF
DQ9
DQ11
DQS1#
DQ13
DQ15
A7
VSS
VDD
VDD
VSS
A17
DQ23
DQ21
DQS2#
DQ19
DQ17
VREF
4
VSS
VSSQ
VDDQ
VSSQ
VDDQ
VSSQ
VDD
VSS
VDD
VDD
VSS
VDD
VSSQ
VDDQ
VSSQ
VDDQ
VSSQ
VSS
5
6
7
8
9
VSS
VSSQ
VDDQ
VSSQ
VDDQ
VSSQ
VDD
VSS
VDD
VDD
VSS
VDD
VSSQ
VDDQ
VSSQ
VDDQ
VSSQ
VSS
10
VEXT
DQ1
DQ3
DQS0#
DQ5
DQ7
A2
VSS
VDD
VDD
VSS
A12
DQ31
DQ29
DQS3#
DQ27
DQ25
VEXT
11
TMS
DQ0
DQ2
DQS0
DQ4
DQ6
A1
A4
B0
B1
A14
A11
DQ30
DQ28
DQS3
DQ26
DQ24
TDO
12
TCK
VSS
VSS
VSS
VSS
DVLD
A0
A3
CK
CK#
A13
A10
NF1
VSS
VSS
VSS
VSS
TDI
Notes: 1. No Function. This signal is internally connected and has parasitic characteristics of an
address input signal. This may optionally be connected to GND.
Table 3:
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
16 Meg x 16 Ball Assignment (Top View) 144-Ball µBGA
1
VSS
VSS
VSS
VSS
VSS
DM0
A5
A8
AS#
WE#
A19
A15
DM1
VSS
VSS
VSS
VSS
VSS
2
VEXT
NF1
NF1
NF2
NF1
NF1
A6
A9
B2
REF#
CS#
A16
NF1
NF1
NF1
NF1
NF1
VEXT
3
VREF
NF1
NF1
NF2
NF1
NF1
A7
VSS
VDD
VDD
VSS
A17
NF1
NF1
NF2
NF1
NF1
VREF
4
VSS
VSSQ
VDDQ
VSSQ
VDDQ
VSSQ
VDD
VSS
VDD
VDD
VSS
VDD
VSSQ
VDDQ
VSSQ
VDDQ
VSSQ
VSS
5
6
7
8
9
VSS
VSSQ
VDDQ
VSSQ
VDDQ
VSSQ
VDD
VSS
VDD
VDD
VSS
VDD
VSSQ
VDDQ
VSSQ
VDDQ
VSSQ
VSS
10
VEXT
DQ1
DQ3
DQS0#
DQ5
DQ7
A2
VSS
VDD
VDD
VSS
A12
DQ15
DQ13
DQS1#
DQ11
DQ9
VEXT
11
TMS
DQ0
DQ2
DQS0
DQ4
DQ6
A1
A4
B0
B1
A14
A11
DQ14
DQ12
DQS1
DQ10
DQ8
TDO
12
TCK
VSS
VSS
VSS
VSS
DVLD
A0
A3
CK
CK#
A13
A10
A18
VSS
VSS
VSS
VSS
TDI
Notes: 1. No Function. This signal is internally connected and has parasitic characteristics of an I/O
signal. This may optionally be connected to GND.
2. No Function. This signal is internally connected and has parasitic characteristics of an DQS
signal. This may optionally be connected to GND.
pdf: 09005aef81121545/source: 09005aef810c0ffc
256Mbx16x32RLDRAM_2.fm - Rev F 8/05 EN
7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001 Micron Technology, Inc. All rights reserved.
256Mb: x16, x32 2.5V VEXT, 1.8V VDD, 1.8V VDDQ, RLDRAM
Ball Assignment and Description
Table 4:
Ball Descriptions
Symbol
Type
Description
CK, CK#
Input
CS#
Input
AS#, WE#, REF#
Input
A[0:19]
Input
BA[0:2]
DQ[0:31]
Input
Input/
Output
DQSx, DQSx#
Output
DVLD
Output
DM0, DM1
Input
TMS
TDI
TCK
Input
Input
TDO
VREF
Output
Input
VEXT
VDD
VDDQ
Supply
Supply
Supply
VSS
VSSQ
NF
Supply
Supply
–
Input clock: CK and CK# are differential clock inputs. Addresses and commands are latched
on the rising edge of CK, input data is latched on both edges of CK. CK# is ideally 180
degrees out of phase with CK.
Chip select: CS# enables the command decoder when low and disables it when high. When
the command decoder is disabled, new commands are ignored, but internal operations
continue.
Command inputs: Sampled at the positive edge of CK, AS#, WE#, and REF# define (together
with CS#) the command to be executed.
Address inputs: A[0:19] define the row and column addresses for READ and WRITE
operations. During a MODE REGISTER SET, the address inputs define the register settings.
They are sampled at the rising edge of CK. In the x32 configuration, A[19] is not used. Refer
to Table 5 on page 9 for burst length considerations.
Bank address inputs: Select to which internal bank a command is being applied.
Data input/output: The DQ signals form the 32-bit data bus. During READ commands, the
data is referenced to both edges of DQS/DQS#. During WRITE commands, the data is
sampled at both edges of CK.
Data read strobes: DQSx and DQSx# are the differential data read strobes. During READs,
they are transmitted by the RLDRAM and edge-aligned with data. DQSx# is ideally 180
degrees out of phase with DQSx. DQS0 and DQS0# are aligned with DQ0–DQ7. DQS1 and
DQS1# are aligned with DQ8–DQ15. DQS2 and DQS2# are aligned with DQ16–DQ23. DQS3
and DQS3# are aligned with DQ24–DQ31.
Data valid: The DVLD indicates valid output data. DVLD is edge-aligned with DQSx and
DQSx#.
Input data mask: DM0 and DM1 are the input mask signal for WRITE data. The first half of
the input data burst is masked when DM0 is sampled HIGH along with the WRITE
command. The second half of the input data burst is masked when DM1 is sampled HIGH
along with the WRITE command.
IEEE 1149.1 test inputs: JEDEC-standard 1.8V I/O levels. These balls may be left as no connect
if the JTAG function is not used in the circuit.
IEEE 1149.1 clock input: JEDEC-standard 1.8V I/O levels. This ball must be tied to VSS if the
JTAG function is not used in the circuit.
IEEE 1149.1 test output: JEDEC-standard 1.8V I/O level.
Input reference voltage: Nominally VDDQ/2. Provides a reference voltage for the input
buffers.
Power supply: 2.5V nominal. See Table 19 on page 35 for range.
Power supply: 1.8V nominal. See Table 19 on page 35 for range.
Power supply: Isolated Output Buffer Supply. Nominally, 1.8V. See Table 19 on page 35 for
range.
Power supply: GND.
Power supply: Isolated Output Buffer Supply. GND.
No function: These balls may be connected to ground.
pdf: 09005aef81121545/source: 09005aef810c0ffc
256Mbx16x32RLDRAM_2.fm - Rev F 8/05 EN
8
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001 Micron Technology, Inc. All rights reserved.
256Mb: x16, x32 2.5V VEXT, 1.8V VDD, 1.8V VDDQ, RLDRAM
Commands
Commands
According to the functional signal description, the following command sequences are
possible. All input states or sequences not shown are illegal or reserved. All command
and address inputs must meet setup and hold times around the rising edge of CK.
Table 5:
Address Widths at Different Burst Lengths
Burst Length
x32
x16
BL = 2
BL = 4
18:0
17:0
19:0
18:0
Table 6:
Command Table
Note 1
Operation
READ cycle
WRITE cycle
NOP: no operation
DESELECT
AUTO REFRESH
MRS: mode register set4
CS#
AS#
WE#
REF#
A[19:0]2, 3
B[2:0]
DM[1:0]
L
L
L
H
L
L
L
L
H
X
H
L
H
L
H
X
H
L
H
H
H
X
L
L
VALID
VALID
X
X
X
VALID
VALID
VALID
X
X
VALID
X
X
VALID
X
X
X
X
Notes: 1. X represents a “Don’t Care”
H represents a logic HIGH
L represents a logic LOW
A represents a valid address
BA represents a valid bank address.
2. In the x32 configuration A19 is not used.
3. See above table; address widths at different burst lengths.
4. Only A(17:0) are used for the MRS command.
pdf: 09005aef81121545/source: 09005aef810c0ffc
256Mbx16x32RLDRAM_2.fm - Rev F 8/05 EN
9
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001 Micron Technology, Inc. All rights reserved.
256Mb: x16, x32 2.5V VEXT, 1.8V VDD, 1.8V VDDQ, RLDRAM
Commands
Table 7:
Description of Commands
Command
1
DESEL/NOP
MRS
READ
WRITE
AREF
Description
The NOP command is used to perform a no operation to the RLDRAM, which essentially deselects
the chip. Use the NOP command to prevent unwanted commands from being registered during idle
or wait states. Operations already in progress are not affected. Output values depend on command
history.
The mode register is set via the address inputs A(17:0). See Figure 9 on page 15 for further
information. The MRS command can only be issued when all banks are idle and no bursts are in
progress.
The READ command is used to initiate a burst read access to a bank. The value on the BA(2:0) inputs
selects the bank, and the address provided on inputs A(19:0) selects the data location within the
bank.
The WRITE command is used to initiate a burst write access to a bank. The value on the BA(2:0)
inputs selects the bank, and the address provided on inputs A(19:0) selects the data location within
the bank. Input data appearing on the DQs is written to the memory array subject to the DMx input
logic level appearing coincident with the WRITE command. If the DM0 signal is registered LOW, the
first half of the burst WRITE data will be written to memory, if registered HIGH, the corresponding
data inputs will be ignored (i.e., this part of the data word will not be written). If the DM1 signal is
registered LOW, the second half of the burst WRITE data will be written to memory, if registered
HIGH, the corresponding data inputs will be ignored (i.e., this part of the data word will not be
written).
The AREF is used during normal operation of the RLDRAM to refresh the memory content of a bank.
The command is nonpersistent, so it must be issued each time a refresh is required. The value on the
BA(2:0) inputs selects the bank. The refresh address is generated by an internal refresh controller,
effectively making each address bit a “Don’t Care” during the AREF command. The RLDRAM
requires 64K cycles at an average periodic interval of 0.49µs 2(MAX). To improve efficiency, eight
AREF commands (one for each bank) can be posted to the RLDRAM at periodic intervals of 3.9µs.3
Notes: 1. When the chip is deselected, internal NOP commands are generated and no commands are
accepted.
2. Actual refresh is 32ms/8K/8 = 0.488µs.
3. Actual refresh is 32ms/8k = 3.90µs.
pdf: 09005aef81121545/source: 09005aef810c0ffc
256Mbx16x32RLDRAM_2.fm - Rev F 8/05 EN
10
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001 Micron Technology, Inc. All rights reserved.
256Mb: x16, x32 2.5V VEXT, 1.8V VDD, 1.8V VDDQ, RLDRAM
Commands
Table 8:
AC Electrical Characteristics
Note 1
-33
Description
Symbol
Min
-4
Max
Min
-5
Max
Min
Max
Units
Notes
2
200
0.55
0.55
ns
MHz
t
CK
t
CK
tCK
Clock
Clock cycle time
System frequency
Clock HIGH time
Clock LOW time
Mode register set cycle time to any
command
t
CK
CK
t
CKH
t
CKL
tMRSC
3.3
0.45
0.45
4
tAS/tCS
1.0
1.0
1.0
ns
tDS
0.5
0.5
0.5
ns
tAH/tCH
1.0
1.0
1.0
ns
tDH
0.5
0.5
0.5
ns
tDQSH
0.4
0.4
2.4
f
4.0
300
0.55
0.55
5.0
0.45
0.45
4
250
0.55
0.55
0.45
0.45
4
Setup Times3
Address/command and input setup
time
Data-in and data mask to DK setup
time
Hold Times
Address/command and input hold
time
Data-in and data mask to DK hold
time
Data and Data Strobe
DQS, DQS# HIGH time
DQS, DQS# LOW time
Clock to DQS, DQS#
DQS to output valid
DQS to output High-Z
DQS to DVLD
tDQSL
tCKDQS
tDQSQ
tQSQHZ
tQSVLD
-0.4
0.6
0.6
3.9
0.35
0.4
0.4
0.4
0.4
2.4
-0.4
0.6
0.6
3.9
0.35
0.4
0.4
0.4
0.4
2.4
-0.4
0.6
0.6
3.9
0.35
0.4
0.4
tCK
tCK
ns
ns
ns
ns
4
5
Notes: 1. All timing parameters are measured relative to the crossing point of CK/CK# and to the
crossing point with VREF of the command and address signals.
2. CK/CK# input slew rate must be >1V/ns (>2V/ns if measured differentially).
3. The signal input slew rate must be >1V/ns.
4. Parameter only valid within one DQS/DQ group, e.g., DQS0, DQS0#, and DQ0–DQ7; DQS1,
DQS1#, and DQ8–DQ15.
5. The rising and falling edges of DVLD are referenced to falling edges of DQS.
Figure 4:
Clock Command/Address Timings
tCK
tCKH
tCKL
CK#
CK
CMD,
ADDR
VALID
VALID
VALID
tAS, tCS tAH, tCH
DON’T CARE
pdf: 09005aef81121545/source: 09005aef810c0ffc
256Mbx16x32RLDRAM_2.fm - Rev F 8/05 EN
11
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001 Micron Technology, Inc. All rights reserved.
256Mb: x16, x32 2.5V VEXT, 1.8V VDD, 1.8V VDDQ, RLDRAM
Initialization
Initialization
The RLDRAM must be powered up and initialized in a predefined manner. Operational
procedures other than those specified may result in undefined operations or permanent
damage to the device.
The following sequence is used for Power-Up:
1. Apply power (VEXT, VDD, VDDQ, VREF ) and start clock as soon as the supply voltages
are stable. Apply VDD and VEXT before or at the same time as VDDQ. Apply VDDQ
before or at the same time as VREF. Although there is no timing relation between VEXT
and VDD, the chip starts the power-up sequence only after both voltages are at their
nominal levels. The pad supply must not be applied before the core supplies. CK/CK#
must meet VID(DC) prior to being applied. Maintain all remaining balls in NOP conditions.
2. Maintain stable conditions for 200µs (MIN).
3. Issue three MODE REGISTER Set commands: two dummies plus one valid MRS. It is
recommended that the dummy MRS commands are the same value as the desired
MRS.
4. tMRSC after the valid MRS, issue eight AUTO REFRESH commands, one on each bank
and separated by 2,048 cycles. Initial bank refresh order does not matter.
5. After tRC, the chip is ready for normal operation.
Figure 5:
Power-Up Sequence
VEXT
VDD
VDDQ
VREF
CK#
CK
CMD
NOP
NOP
MRS
MRS
MRS
NOP
RF0
RF1
RF7
AC
ADD
200µs MIN
tMRSC2
2,048
cycles
MIN3
6 × 2,048
cycles
MIN3
tRC
DON’T CARE
Notes: 1. MRS: MRS command
RFx: REFRESH Bank x
AC: any command.
2. During tMRSC, NOP command must be given on the rising edge of CK.
3. When the RLDRAM is powered up with the matched impedance mode inactive, the 2,048
cycles between the eight REFRESH commands are not required. These cycles are necessary
in order to calibrate the output drivers.
pdf: 09005aef81121545/source: 09005aef810c0ffc
256Mbx16x32RLDRAM_2.fm - Rev F 8/05 EN
12
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001 Micron Technology, Inc. All rights reserved.
256Mb: x16, x32 2.5V VEXT, 1.8V VDD, 1.8V VDDQ, RLDRAM
Initialization
Table 9:
Clock Input Operating Conditions
Notes 1–8
Parameter/Condition
Clock input voltage level; CK and CK#
Clock input differential voltage; CK and CK#
Clock input differential voltage; CK and CK#
Clock input crossing point voltage; CK and CK#
Figure 6:
Symbol
Min
Max
Units
Notes
VIN(DC)
VID(DC)
VID(AC)
VIX(AC)
-0.3
0.3
0.6
VDDQ/2 - 0.15
VDDQ + 0.3
VDDQ + 0.6
VDDQ + 0.6
VDDQ/2 + 0.15
V
V
V
V
9
9
10
Clock Input
VIN(DC) MAX
Maximum Clock Level
CK#
X
VDDQ/2 + 0.15
VDDQ/2
VIX(AC) MAX
VID(AC)
11
X
VDDQ/2 - 0.15
13
VID(DC) 12
VIX(AC) MIN
CK
Minimum Clock Level
VIN(DC) MIN
Notes: 1. DQSx and DQSx# have the same requirements as CK and CK#.
2. All voltages referenced to VSS.
3. Tests for AC timing, IDD, and electrical AC and DC characteristics may be conducted at
nominal reference/supply voltage levels, but the related specifications and device operations are tested for the full voltage range specified.
4. Outputs (except for IDD measurements) measured with equivalent load.
5. AC timing and IDD tests may use a VIL-to-VIH swing of up to 1.5V in the test environment,
but input timing is still referenced to VREF (or to the crossing point for CK/CK#), and
parameter specifications are tested for the specified AC input levels under normal use conditions. The minimum slew rate for the input signals used to test the device is ≥1V/ns in the
range between VIL(AC) and VIH(AC).
6. The AC and DC input level specifications are as defined in the HSTL Standard (i.e., the
receiver will effectively switch as a result of the signal crossing the AC input level, and will
remain in that state as long as the signal does not ring back above [below] the DC input
LOW [HIGH] level).
7. The CK/CK# input reference level (for timing referenced to CK/CK#) is the point at which
CK and CK# cross. The input reference level for signals other than CK/CK# is VREF.
8. CK and CK# input slew rate must be ≥1V/ns (≥2V/ns if measured differentially).
9. VID is the magnitude of the difference between the input level on CK and the input level
on CK#.
10. The value of VIX is expected to equal VDDQ/2 of the transmitting device and must track
variations in the DC level of the same.
11. CK and CK# must cross within this region.
12. CK and CK# must meet at least VID(DC) MIN when static and centered around VDDQ/2.
13. Minimum peak-to-peak swing.
pdf: 09005aef81121545/source: 09005aef810c0ffc
256Mbx16x32RLDRAM_2.fm - Rev F 8/05 EN
13
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001 Micron Technology, Inc. All rights reserved.
256Mb: x16, x32 2.5V VEXT, 1.8V VDD, 1.8V VDDQ, RLDRAM
Mode Register Set Command (MRS)
Mode Register Set Command (MRS)
The mode register stores the data for controlling the operating modes of the memory. It
programs the RLDRAM configuration, burst length, and I/O options. During a MODE
REGISTER SET command, the address inputs A(17:0) are sampled and stored in the
mode register. tMRSC must be met before any command can be issued to the RLDRAM.
The mode register may be set at any time during device operation. However, any pending operations are not guaranteed to successfully complete.
Figure 7:
Mode Register Set
CK#
CK
CS#
AS#
WE#
REF#
A(17:0)
COD
A(19:18)
BA(2:0)
DON’T CARE
Note:
Figure 8:
COD: code to be loaded into the register
Mode Register Set Timing
CK#
CK
CMD
MRS
NOP
NOP
AC
tMRSC
DON’T CARE
Note:
pdf: 09005aef81121545/source: 09005aef810c0ffc
256Mbx16x32RLDRAM_2.fm - Rev F 8/05 EN
MRS: MRS command
AC: any command.
14
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256Mb: x16, x32 2.5V VEXT, 1.8V VDD, 1.8V VDDQ, RLDRAM
Mode Register Set Command (MRS)
Figure 9:
Mode Register Bit Map
A(17:6)
A5
A4
A3
A2
Reserved1
Driver
Strength
Matched
Mode
Burst
Length
A1
A0
Configuration
A5
Driver Strength2
A3
Burst Length
A2
A1
A0
RLDRAM
Configuration
0
8mA (default)
0
2 (default)
0
0
0
32 (default)
1
4
0
0
1
12
0
1
0
2
1
Reserved
A4
Matched Mode
0
Inactive (default)
1
Active3
0
1
1
3
1
0
0
4
1
0
1
Reserved
1
1
0
Reserved
1
1
1
Reserved
Notes: 1. Bits A(17:6) must be set to zero.
2. HSTL-compliant current specification.
3. Automatic I/O impedance calibration is activated in matched mode.
pdf: 09005aef81121545/source: 09005aef810c0ffc
256Mbx16x32RLDRAM_2.fm - Rev F 8/05 EN
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256Mb: x16, x32 2.5V VEXT, 1.8V VDD, 1.8V VDDQ, RLDRAM
Configuration Table
Configuration Table
The table below shows the different RLDRAM configurations that can be programmed
into the mode register for different operating frequencies. The READ and WRITE latency
(tRL and tWL) values, along with the row cycle times (tRC), are shown in clock cycles, as
well as in nanoseconds. The shaded areas correspond to configurations that are not
allowed.
Table 10:
RLDRAM Configuration Table
Configuration
Frequency
Symbol
t
300 MHz
250 MHz
200 MHz
RC
tRL
tWL (BL = 2)
tWL (BL = 4)
tRC
tRL
tWL (BL = 2)
tWL (BL = 4)
tRC
tRL
tWL (BL = 2)
tWL (BL = 4)
tRC
tRL
tWL (BL = 2)
tWL (BL = 4)
pdf: 09005aef81121545/source: 09005aef810c0ffc
256Mbx16x32RLDRAM_2.fm - Rev F 8/05 EN
1
2
3
4
Units
5
5
2
1
6
5
2
1
7
5
2
1
30.0
25.0
10.0
5.0
28.0
20.0
8.0
4.0
35.0
25.0
10.0
5.0
8
6
3
2
26.7
20.0
10.0
6.7
32.0
24.0
12.0
8.0
40.0
30.0
15.0
10.0
Cycles
Cycles
Cycles
Cycles
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
25.0
25.0
10.0
5.0
16
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Write Basic Information
Write Basic Information
Write accesses are initiated with a WRITE command, as shown in the Figure 10. Row and
bank addresses are provided together with the WRITE command.
During WRITE commands, data will be registered at both edges of CK according to the
programmed burst length (BL). The first valid data will be registered with the first rising
CK edge WL cycles after the WRITE command has been issued.
Any WRITE burst may be followed by a subsequent READ command. Figure 16 on
page 20 illustrates the timing requirements for a WRITE followed by a READ for burst of
four.
Setup and hold times for incoming DQ relative to the CK edges are specified as tDS and
tDH.
The first or second part of the incoming data burst is masked if the corresponding DMx
signal is sampled HIGH along with the WRITE command. The setup and hold times for
data mask are the same as for address and command.
Figure 10:
WRITE Command
CS#
AS#
WE#
REF#
DM(1:0)
DM
A(20:0)
A
BA(2:0)
BA
DON’T CARE
Note:
Figure 11:
A: address
BA: bank address
DM: data mask.
Basic WRITE Burst Timing
CK#
CK
Write
Latency
DQ
tDS tDH
D0
tDS tDH
D1
D2
D3
DON’T CARE
pdf: 09005aef81121545/source: 09005aef810c0ffc
256Mbx16x32RLDRAM_2.fm - Rev F 8/05 EN
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256Mb: x16, x32 2.5V VEXT, 1.8V VDD, 1.8V VDDQ, RLDRAM
Write Basic Information
Table 11:
Timing Parameters
-33
-4
-5
Symbol
Min/Max
Min/Max
Min/Max
Units
tDS
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
t
Figure 12:
DH
WRITE Burst Basic Sequence: BL = 2; WL = 3
0
1
2
3
4
5
6
7
8
CMD
WR
WR
WR
WR
WR
WR
WR
WR
WR
ADDR
A
BA0
A
BA1
A
BA2
A
BA3
A
BA4
A
BA5
A
BA6
A
BA7
A
BA0
CK#
CK
WL = 3
D0a D0b D1a D1b D2a D2b D3a D3b D4a D4b D5a
DQ
D5
DON’T CARE
Figure 13:
WRITE Burst Basic Sequence: BL = 4; WL = 2
0
1
2
3
4
5
6
7
8
CMD
WR
NOP
WR
NOP
WR
NOP
WR
NOP
WR
ADDR
A
BA0
CK#
CK
A
BA1
A
BA2
A
BA3
A
BA0
WL = 2
D0a D0b
DQ
D0c
D0d D1a D1b
D1c
D1d D2a D2b
D2c
D2d D3a
D3
DON’T CARE
Notes: 1. A/BAx: address A of bank x
WR: WRITE
Dxy: data y to bank x
WL: WRITE latency.
2. Any free bank may be used in any given CMD. The sequence shown is only one example of
a bank sequence.
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256Mbx16x32RLDRAM_2.fm - Rev F 8/05 EN
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256Mb: x16, x32 2.5V VEXT, 1.8V VDD, 1.8V VDDQ, RLDRAM
Write Basic Information
Figure 14:
WRITE Data Mask Timing: BL = 2; WL = 2
0
1
2
3
4
5
6
7
8
CMD
WR
WR
WR
WR
WR
WR
WR
WR
WR
ADDR
A
BA0
A
BA1
A
BA2
A
BA3
A
BA4
A
BA5
A
BA6
A
BA7
A
BA0
D0a D0b
D1a D1b D2a D2b D3a D3b D4a D4b D5a D5b D6a
CK#
CK
WL = 2
DM0
DM1
DQ
Data
masked
D6
DON’T CARE
Notes: 1. A/BAx: address A of bank x
WR: WRITE
Dxy: data y to bank x
WL: WRITE latency.
2. Any free bank may be used in any given CMD. The sequence shown is only one example of
a bank sequence.
pdf: 09005aef81121545/source: 09005aef810c0ffc
256Mbx16x32RLDRAM_2.fm - Rev F 8/05 EN
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256Mb: x16, x32 2.5V VEXT, 1.8V VDD, 1.8V VDDQ, RLDRAM
Write Basic Information
Figure 15:
Write Data Mask Timing: BL = 4; WL = 1
0
1
2
3
4
5
6
7
8
CMD
WR
NOP
WR
NOP
WR
NOP
WR
NOP
WR
ADDR
A
BA0
CK#
CK
A
BA2
A
BA4
A
BA6
A
BA0
WL = 1
DM0
DM1
DQ
D0a D0b
D0c
D0d D2a D2b
D2c
D2d D4a D4b
D4c
D4d D6a D6b
D6c
D6
Data
masked
Figure 16:
WRITE followed by READ: BL = 4; RL = 5; WL = 1
0
1
2
3
4
5
6
7
8
9
CMD
WR
RD
WR
RD
NOP
NOP
NOP
NOP
NOP
NOP
ADDR
A
BA0
A
BA1
A
BA3
A
BA2
CK#
CK
RL = 5
WL = 1
D0a
DQ
D0b
D0c
D0d D3a
D3b
D3c
D3d
Q1a Q1b Q1c
Q1d Q2a Q1d Q2a
DQSx
DQSx#
DON’T CARE
Note:
pdf: 09005aef81121545/source: 09005aef810c0ffc
256Mbx16x32RLDRAM_2.fm - Rev F 8/05 EN
UNDEFINED
A/BAx: address A of bank x
WR: WRITE
Dxy: data y to bank x
WL: WRITE latency
RD: READ
Qxy: data y from bank x
RL: READ latency.
20
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256Mb: x16, x32 2.5V VEXT, 1.8V VDD, 1.8V VDDQ, RLDRAM
Read Basic Information
Read Basic Information
Read accesses are initiated with a READ command, as shown in Figure 17. Row and
bank addresses are provided with the READ command.
During READ bursts, the memory device drives the read data edge-aligned with the DQS
signal. After a programmable READ latency, data is available at the outputs. The data
valid signal indicates that valid data will be present in the next half clock cycle.
The skew between DQS and the crossing point of CK is specified as tCKDQS. tDQSQ is
the skew between DQS and the last valid data edge considered over all the data generated at the DQ signals. tDQSQ is derived at each DQS clock edge and is not cumulative
over time.
After completion of a burst, assuming no other commands have been initiated, output
data (DQ) will go to High-Z. Back-to-back READ commands are possible, producing a
continuous flow of output data.
The data valid window is derived from each DQS transition and is defined as:
MIN (tCKH, tCKL) - 2 tDQSQ(MAX)
Any READ burst may be followed by a subsequent WRITE command. Figures 21–24 on
page 24–25 illustrate the timing requirements for a READ followed by a WRITE. Depending on the programmed READ latency, a READ-to-WRITE delay occurs in order to prevent bus contention. Some systems having long line lengths or severe skews may need
additional idle cycles inserted.
Figure 17:
READ Command
CK#
CK
CS#
AS#
WE#
REF#
A(20:0)
A
BA(2:0)
BA
DON’T CARE
Note:
pdf: 09005aef81121545/source: 09005aef810c0ffc
256Mbx16x32RLDRAM_2.fm - Rev F 8/05 EN
A: address
BA: bank address.
21
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256Mb: x16, x32 2.5V VEXT, 1.8V VDD, 1.8V VDDQ, RLDRAM
Read Basic Information
Figure 18:
Basic READ Burst Timing
tCKH
tCKL
tCK
CK#
CK
tDQSL
tCKDQS
tDQSH
DQSx
DQS#
tQSVLD
tQSVLD
DVLD
DQ
Q0
Q1
Q2
Q3
tDQSQ
tQSQHZ
tDQSQ
Note 1
UNDEFINED
Table 12:
Timing Parameters
-33
Symbol
Min
tCK
3.3
0.45
0.45
2.4
tCKH
tCKL
tCKDQS
tDQSQ
tQSQHZ
tQSVLD
t
-0.4
0.4
0.4
DQSH
tDQSL
Note:
pdf: 09005aef81121545/source: 09005aef810c0ffc
256Mbx16x32RLDRAM_2.fm - Rev F 8/05 EN
-4
Max
Min
4.0
0.45
0.45
2.4
0.55
0.55
3.9
0.35
0.4
0.4
0.6
0.6
-0.4
0.4
0.4
-5
Max
0.55
0.55
3.9
0.35
0.4
0.4
0.6
0.6
Min
5.0
0.45
0.45
2.4
-0.4
0.4
0.4
Max
Units
0.55
0.55
3.9
0.35
0.4
0.4
0.6
0.6
tCK
ns
tCK
ns
ns
ns
ns
tCK
tCK
Minimum data valid window can be expressed as MIN (tCKH, tCKL) - 2 × tDQSQ (MAX).
22
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Read Basic Information
Figure 19:
READ Burst: BL = 2; RL = 5
0
1
2
3
4
5
6
7
8
CMD
RD
RD
RD
RD
RD
RD
RD
RD
RD
ADDR
A
BA0
A
BA1
A
BA2
A
BA3
A
BA4
A
BA7
A
BA6
A
BA5
A
BA0
CK#
CK
RL = 5
DQSx
DQSx#
DVLD
Q0a Q0b Q1a Q1b Q2a Q2b Q3a
DQ
DON’T CARE
Figure 20:
UNDEFINED
READ Burst: BL = 4; RL = 5
0
1
2
3
4
5
6
7
8
CMD
RD
NOP
RD
NOP
RD
NOP
RD
NOP
RD
ADDR
A
BA0
CK#
CK
A
BA2
A
BA4
A
BA6
A
BA1
RL = 5
DQSx
DQSx#
DVLD
DQ
Q0a Q0b Q0c Q0d Q2a Q2b Q2c
DON’T CARE
Note:
pdf: 09005aef81121545/source: 09005aef810c0ffc
256Mbx16x32RLDRAM_2.fm - Rev F 8/05 EN
UNDEFINED
A/BAx: address A of bank x
Dxy: data y to bank x
RC: row cycle time
RL: READ latency.
23
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256Mb: x16, x32 2.5V VEXT, 1.8V VDD, 1.8V VDDQ, RLDRAM
Read Basic Information
Figure 21:
READ followed by WRITE: BL = 2; RL = 5; WL = 2
0
1
2
3
4
5
6
7
8
9
CMD
RD
NOP
NOP
NOP
NOP
WR
WR
NOP
NOP
NOP
ADDR
A
BA0
A
BA1
A
BA2
D1a D1b
D2a D2b
CK#
CK
RL = 5
WL = 2
DQ
Q0a Q0b
DVLD
DQSx
DQSx#
DON’T CARE
Figure 22:
UNDEFINED
READ followed by WRITE: BL = 2; RL = 5; WL = 2 – Interleaved Data
0
1
2
3
4
5
6
7
8
9
CMD
RD
WR
NOP
NOP
NOP
WR
NOP
NOP
NOP
NOP
ADDR
A
BA0
A
BA1
CK#
CK
A
BA2
RL = 5
WL = 2
DQ
WL = 2
Q0a Q0b
D1a D1b
D2a D2b
DVLD
DQSx
DQSx#
DON’T CARE
Note:
pdf: 09005aef81121545/source: 09005aef810c0ffc
256Mbx16x32RLDRAM_2.fm - Rev F 8/05 EN
UNDEFINED
A/BAx: address A of bank x
Dxy: data y to bank x
RD: READ
RL: READ latency
WL: WRITE latency.
24
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256Mb: x16, x32 2.5V VEXT, 1.8V VDD, 1.8V VDDQ, RLDRAM
Read Basic Information
Figure 23:
READ followed by WRITE: BL = 4; RL = 5; WL = 1
0
1
2
3
4
5
6
7
8
9
CMD
RD
NOP
NOP
NOP
NOP
NOP
NOP
WR
NOP
NOP
ADDR
A
BA0
D1a D1b
D1c
CK#
CK
A
BA1
RL = 5
WL = 1
Q0a Q0b
DQ
Q0c Q0d
D1
DVLD
DQSx
DQSx#
DON’T CARE
Figure 24:
UNDEFINED
READ followed by WRITE: BL = 4; RL = 5; WL = 1 – Interleaved Data
0
1
2
3
4
5
6
7
8
9
CMD
RD
WR
NOP
NOP
NOP
NOP
NOP
WR
NOP
NOP
ADDR
A
BA0
A
BA1
D2a D2b
D2c
CK#
CK
A
BA2
RL = 5
WL = 1
WL = 1
D1a D1b D1a D1b
DQ
Q0a Q0b
Q0c Q0d
D2
DVLD
DQSx
DQSx#
DON’T CARE
Note:
pdf: 09005aef81121545/source: 09005aef810c0ffc
256Mbx16x32RLDRAM_2.fm - Rev F 8/05 EN
UNDEFINED
A/BAx: address A of bank x
Dxy: data y to bank x
RD: READ
RL: READ latency
WL: WRITE latency.
25
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256Mb: x16, x32 2.5V VEXT, 1.8V VDD, 1.8V VDDQ, RLDRAM
AUTO REFRESH Command (AREF)
AUTO REFRESH Command (AREF)
AREF is used to perform a REFRESH cycle on 1 row in a specific bank. The row addresses
are generated by an internal refresh counter for each bank; external address balls are
“DON’T CARE.” The delay between the AREF command and a subsequent command to
the same bank must be at least tRC.
Within a period of 32ms (tREF), the entire memory must be refreshed. Figure 25 illustrates an example of a continuous refresh sequence. Other refresh strategies, such as
burst refresh, are also possible.
Figure 25:
AUTO REFRESH Command
CK#
CK
CS#
AS#
WE#
REF#
A(20:0)
BA(2:0)
BA
DON’T CARE
Note:
Figure 26:
BA: Bank address.
AUTO REFRESH Cycle
CK#
CK
CMD
ARFx
ACy
ACx
ACy
ARFx
ACy
tRC
DON’T CARE
Notes: 1. ACx: any command on bank x
ARFx: auto refresh bank x
ACy: any command on different bank.
2. tRC is configuration-dependent. Refer to Table 10 on page 16.
pdf: 09005aef81121545/source: 09005aef810c0ffc
256Mbx16x32RLDRAM_2.fm - Rev F 8/05 EN
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256Mb: x16, x32 2.5V VEXT, 1.8V VDD, 1.8V VDDQ, RLDRAM
IEEE 1149.1 Serial Boundary Scan (JTAG)
IEEE 1149.1 Serial Boundary Scan (JTAG)
The RLDRAM incorporates a serial boundary scan Test Access Port (TAP). This port
operates in accordance with IEEE Standard 1149.1-1990 but does not have the set of
functions required for full 1149.1 compliance. These functions from the IEEE specification are excluded because their inclusion places an added delay in the critical speed
path of the RLDRAM. Note that the TAP controller functions in a manner that does not
conflict with the operation of other devices using 1149.1 fully compliant TAPs. The TAP
operates using JEDEC-standard 1.8V I/O logic levels.
The RLDRAM contains a TAP controller, instruction register, boundary scan register,
bypass register, and ID register.
Disabling The JTAG Feature
It is possible to operate the RLDRAM without using the JTAG feature. To disable the TAP
controller, TCK must be tied LOW (VSS) to prevent clocking of the device. TDI and TMS
are internally pulled up and may be unconnected. They may alternately be connected to
VDD through a pull-up resistor. TDO should be left unconnected. Upon power-up, the
device will come up in a reset state which will not interfere with the operation of the
device.
Test Access Port (TAP)
Test Clock (TCK)
The test clock is used only with the TAP controller. All inputs are captured on the rising
edge of TCK. All outputs are driven from the falling edge of TCK.
Test Mode Select (TMS)
The TMS input is used to give commands to the TAP controller and is sampled on the
rising edge of TCK. It is allowable to leave this ball unconnected if the TAP is not used.
The ball is pulled up internally, resulting in a logic HIGH level.
Test Data-in (TDI)
The TDI ball is used to serially input information into the registers and can be connected
to the input of any of the registers. The register between TDI and TDO is chosen by the
instruction that is loaded into the TAP instruction register. For information on loading
the instruction register, see Figure 27 on page 28. TDI is internally pulled up and can be
unconnected if the TAP is unused in an application. TDI is connected to the most significant bit (MSB) of any register. (See Figure 28 on page 29.)
pdf: 09005aef81121545/source: 09005aef810c0ffc
256Mbx16x32RLDRAM_2.fm - Rev F 8/05 EN
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256Mb: x16, x32 2.5V VEXT, 1.8V VDD, 1.8V VDDQ, RLDRAM
Test Access Port (TAP)
Figure 27:
TAP Controller State Diagram
1
TEST-LOGIC
RESET
0
RUN-TEST/
IDLE
0
1
SELECT
DR-SCAN
1
SELECT
IR-SCAN
0
1
0
1
CAPTURE-DR
CAPTURE-IR
0
0
SHIFT-DR
0
SHIFT-IR
1
1
EXIT1-IR
0
1
0
PAUSE-DR
0
PAUSE-IR
1
0
1
0
EXIT2-DR
EXIT2-IR
1
1
UPDATE-DR
1
0
1
EXIT1-DR
0
1
UPDATE-IR
1
0
0
The 0/1 next to each state represents the value of TMS at the rising edge of tCK.
Note:
Test Data-out (TDO)
The TDO output ball is used to serially clock data-out from the registers. The output is
active depending upon the current state of the TAP state machine. (See Figure 27.) The
output changes on the falling edge of TCK. TDO is connected to the least significant bit
(LSB) of any register. (See Figure 28 on page 29.)
Performing A Tap RESET
A RESET is performed by forcing TMS HIGH (VDD) for five rising edges of TCK. This
RESET does not affect the operation of the RLDRAM and may be performed while the
RLDRAM is operating.
At power-up, the TAP is reset internally to ensure that TDO comes up in a High-Z state.
Tap Registers
Registers are connected between the TDI and TDO balls and allow data to be scanned
into and out of the RLDRAM test circuitry. Only one register can be selected at a time
through the instruction register. Data is serially loaded into the TDI ball on the rising
edge of TCK. Data is output on the TDO ball on the falling edge of TCK.
Instruction Register
Three-bit instructions can be serially loaded into the instruction register. This register is
loaded when it is placed between the TDI and TDO balls, as shown in Figure 28. Upon
power-up, the instruction register is loaded with the IDCODE instruction. It is also
loaded with the IDCODE instruction if the controller is placed in a reset state as
described in the previous section.
When the TAP controller is in the Capture-IR state, the two least significant bits are
loaded with a binary “01” pattern to allow for fault isolation of the board-level serial test
data path.
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256Mbx16x32RLDRAM_2.fm - Rev F 8/05 EN
28
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©2001 Micron Technology, Inc. All rights reserved.
256Mb: x16, x32 2.5V VEXT, 1.8V VDD, 1.8V VDDQ, RLDRAM
Test Access Port (TAP)
Bypass Register
To save time when serially shifting data through registers, it is sometimes advantageous
to skip certain chips. The bypass register is a single-bit register that can be placed
between the TDI and TDO balls. This allows data to be shifted through the RLDRAM
with minimal delay. The bypass register is set LOW (VSS) when the BYPASS instruction is
executed.
Boundary Scan Register
The boundary scan register is connected to all the input and bidirectional balls on the
RLDRAM. Several no connect (NC) balls are also included in the scan register to reserve
pins. The RLDRAM has a 104-bit register.
The boundary scan register is loaded with the contents of the RAM I/O ring when the
TAP controller is in the Capture-DR state and is then placed between the TDI and TDO
balls when the controller is moved to the Shift-DR state. The EXTEST, SAMPLE/PRELOAD, and SAMPLE Z instructions can be used to capture the contents of the I/O ring.
The Boundary Scan Order tables (see page 34) show the order in which the bits are connected. Each bit corresponds to one of the balls on the RLDRAM package. The MSB of
the register is connected to TDI, and the LSB is connected to TDO.
Figure 28:
TAP Controller Block Diagram
0
Bypass Register
2 1 0
TDI
Selection
Circuitry
Instruction Register
31 30 29 .
.
Selection
Circuitry
TDO
. 2 1 0
Identification Register
x .
.
.
.
. 2 1 0
Boundary Scan Register
TCK
TAP CONTROLLER
TMS
Note:
x = 103 for all configurations.
Identification (Id) Register
The ID register is loaded with a vendor-specific, 32-bit code during the Capture-DR state
when the IDCODE command is loaded in the instruction register. The IDCODE is hardwired into the RLDRAM and can be shifted out when the TAP controller is in the ShiftDR state. The ID register has a vendor code and other information described in Table 15
on page 33.
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256Mbx16x32RLDRAM_2.fm - Rev F 8/05 EN
29
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001 Micron Technology, Inc. All rights reserved.
256Mb: x16, x32 2.5V VEXT, 1.8V VDD, 1.8V VDDQ, RLDRAM
Tap Instruction Set
Tap Instruction Set
Overview
Eight different instructions are possible with the three-bit instruction register. All combinations are listed in the Instruction Codes table (see page 33). Three of these instructions are listed as RESERVED and should not be used. The other five instructions are
described in detail below.
The TAP controller used in this RLDRAM is not fully compliant to the 1149.1 convention
because some of the mandatory 1149.1 instructions are not fully implemented. The TAP
controller cannot be used to load address, data or control signals into the RLDRAM and
cannot preload the I/O buffers. The RLDRAM does not implement the 1149.1 commands EXTEST or INTEST or the PRELOAD portion of SAMPLE/PRELOAD; rather it performs a capture of the I/O ring when these instructions are executed.
Instructions are loaded into the TAP controller during the Shift-IR state when the
instruction register is placed between TDI and TDO. During this state, instructions are
shifted through the instruction register through the TDI and TDO balls. To execute the
instruction once it is shifted in, the TAP controller needs to be moved into the Update-IR
state.
EXTEST
EXTEST is a mandatory 1149.1 instruction which is to be executed whenever the instruction register is loaded with all zeros. EXTEST is not implemented in the TAP controller,
hence this device is not IEEE 1149.1 compliant.
The TAP controller does recognize an all-0 instruction. When an EXTEST instruction is
loaded into the instruction register, the RLDRAM responds as if a SAMPLE/PRELOAD
instruction has been loaded. EXTEST does not place the RLDRAM outputs in a High-Z
state.
IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the
instruction register. It also places the instruction register between the TDI and TDO
balls and allows the IDCODE to be shifted out of the device when the TAP controller
enters the Shift-DR state.
The IDCODE instruction is loaded into the instruction register upon power-up or whenever the TAP controller is given a test logic reset state.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. The PRELOAD portion of this
instruction is not implemented, so the device TAP controller is not fully 1149.1compliant.
When the SAMPLE/PRELOAD instruction is loaded into the instruction register and the
TAP controller is in the Capture-DR state, a snapshot of data on the inputs and bidirectional balls is captured in the boundary scan register.
The user must be aware that the TAP controller clock can only operate at a frequency up
to 50 MHz, while the RLDRAM clock operates significantly faster. Because there is a large
difference in the clock frequencies, it is possible that during the Capture-DR state, an
input or output will undergo a transition. The TAP may then try to capture a signal while
in transition (metastable state). This will not harm the device, but there is no guarantee
as to the value that will be captured. Repeatable results may not be possible.
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256Mbx16x32RLDRAM_2.fm - Rev F 8/05 EN
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©2001 Micron Technology, Inc. All rights reserved.
256Mb: x16, x32 2.5V VEXT, 1.8V VDD, 1.8V VDDQ, RLDRAM
Tap Instruction Set
To guarantee that the boundary scan register will capture the correct value of a signal,
the RLDRAM signal must be stabilized long enough to meet the TAP controller’s capture
setup plus hold time (tCS plus tCH). The RLDRAM clock input might not be captured
correctly if there is no way in a design to stop (or slow) the clock during a SAMPLE/PRELOAD instruction. If this is an issue, it is still possible to capture all other signals and
simply ignore the value of the CK and CK# captured in the boundary scan register.
Once the data is captured, it is possible to shift out the data by putting the TAP into the
Shift-DR state. This places the boundary scan register between the TDI and TDO balls.
Note that since the PRELOAD part of the command is not implemented, putting the TAP
to the Update-DR state while performing a SAMPLE/PRELOAD instruction will have the
same effect as the Pause-DR command.
BYPASS
When the BYPASS instruction is loaded in the instruction register and the TAP is placed
in a Shift-DR state, the bypass register is placed between TDI and TDO. The advantage of
the BYPASS instruction is that it shortens the boundary scan path when multiple devices
are connected together on a board.
Reserved for Future Use
The remaining 22 instructions are not implemented but are reserved for future use. Do
not use these instructions.
Figure 29:
TAP Timing
1
2
Test Clock
(TCK)
3
tTHTL
tMVTH
tTHMX
tDVTH
tTHDX
t
TLTH
4
5
6
tTHTH
Test Mode Select
(TMS)
Test Data-In
(TDI)
tTLOV
tTLOX
Test Data-Out
(TDO)
DON’T CARE
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256Mbx16x32RLDRAM_2.fm - Rev F 8/05 EN
31
UNDEFINED
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©2001 Micron Technology, Inc. All rights reserved.
256Mb: x16, x32 2.5V VEXT, 1.8V VDD, 1.8V VDDQ, RLDRAM
Tap Instruction Set
Table 13:
TAP AC Electrical Characteristics
Note 1; +0°C ≤ TC ≤ +95°C; +1.7V ≤ VDD ≤ +1.95V
Description
Symbol
Min
Max
Units
Clock
t
THTH
f
TF
t
THTL
tTLTH
Clock cycle time
Clock frequency
Clock HIGH time
Clock LOW time
20
50
10
10
ns
MHz
ns
ns
Output Times
t
TLOX
TLOV
tDVTH
tTHDX
TCK LOW to TDO unknown
TCK LOW to TDO valid
TDI valid to TCK HIGH
TCK HIGH to TDI invalid
0
5
5
ns
ns
ns
ns
5
5
ns
ns
5
5
ns
ns
t
10
Setup Times
tMVTH
TMS setup
Capture setup
tCS
Hold Times
tTHMX
TMS hold
Capture hold
tCH
Notes: 1. tCS and tCH refer to the setup and hold time requirements of latching data from the
boundary scan register
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256Mbx16x32RLDRAM_2.fm - Rev F 8/05 EN
32
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©2001 Micron Technology, Inc. All rights reserved.
256Mb: x16, x32 2.5V VEXT, 1.8V VDD, 1.8V VDDQ, RLDRAM
Tap Instruction Set
Table 14:
TAP DC Electrical Characteristics and Operating Conditions
+0°C ≤ TC ≤ 95°C; +1.7V ≤ VDD ≤ +1.95V, unless otherwise noted
Description
Conditions
Input high (Logic 1) voltage
Input low (Logic 0) voltage
Input leakage current
Output leakage current
Symbol
Min
Max
Units
Notes
VIH
VIL
ILI
ILO
VREF + 0.15
VSSQ - 0.3
-5.0
-5.0
VDD + 0.3
VREF - 0.15
5.0
5.0
V
V
µA
µA
1, 2
1, 2
0.2
0.4
V
V
V
V
1
1
1
1
0V ≤ VIN ≤ VDD
Output disabled,
0V ≤ VIN ≤ VDD
IOLC = 100µA
IOLT = 2mA
|IOHC| = 100µA
|IOHT| = 2mA
Output low voltage
Output low voltage
Output high voltage
Output high voltage
VOL1
VOL2
VOH1
VOH2
VDDQ - 0.2
VDDQ - 0.4
Notes: 1. All voltages referenced to VSS (GND).
2. Overshoot: VIH(AC) ≤ VDD + 0.7V for t ≤ tCK/2.
Undershoot: VIL(AC) ≤ -0.5V for t ≤ tCK/2.
During normal operation, VDDQ must not exceed VDD.
Table 15:
Identification Register Definitions
Instruction Field
All Devices
00ab
REVISION NUMBER
(31:28)
DEVICE ID
(27:12)
MICRON JEDEC ID
CODE (11:1)
ID Register Presence Indicator (0)
Table 16:
Description
ab = 10 for x32, 01 for x16
0000000010100111
00000101100
Allows unique identification of RLDRAM vendor
1
Indicates the presence of an ID register
Scan Register Sizes
Register Name
Bit Size
8
1
32
104
Instruction
Bypass
ID
Boundary Scan
Table 17:
This represents the part number
Instruction Codes
Instruction
Code
EXTEST
0000 0000
SAMPLE/PRELOAD
0000 0101
IDCODE
0010 0001
BYPASS
1111 1111
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256Mbx16x32RLDRAM_2.fm - Rev F 8/05 EN
Description
Captures I/O ring contents. Places the boundary scan register between TDI
and TDO. This instruction is not 1149.1-compliant. This operation does not
affect RLDRAM operations.
Captures I/O ring contents. Places the boundary scan register between TDI
and TDO. This instruction does not implement 1149.1 preload function and
is therefore not 1149.1-compliant.
Loads the ID register with the vendor ID code and places the register
between TDI and TDO. This operation does not affect RLDRAM operations.
Places the bypass register between TDI and TDO. This operation does not
affect RLDRAM operations.
33
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256Mb: x16, x32 2.5V VEXT, 1.8V VDD, 1.8V VDDQ, RLDRAM
Tap Instruction Set
Table 18:
Boundary Scan (Exit) Order
Note 1
Bit#
FBGA Ball
Bit#
FBGA Ball
Bit#
FBGA Ball
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
K1
K2
L2
L1
M1
M3
M2
N1
N3
N3
N2
N2
P3
P3
P2
P2
R2
R3
T2
T2
T3
T3
U2
U2
U3
U3
U10
U10
U11
U11
T10
T10
T11
T11
R10
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
R11
P11
P11
P10
P10
N11
N11
N10
N10
N12
M11
M10
M12
L12
L11
K11
K12
J12
J11
H11
H12
G12
G10
G11
F12
F10
F10
F11
F11
E10
E10
E11
E11
D11
D10
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
C11
C11
C10
C10
B11
B11
B10
B10
B3
B3
B2
B2
C3
C3
C2
C2
D3
D2
E2
E2
E3
E3
F2
F2
F3
F3
F1
G2
G3
G1
H1
H2
J2
J1
Notes: 1. Any unused pins that are in the order will read as a logic “0.”
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256Mbx16x32RLDRAM_2.fm - Rev F 8/05 EN
34
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256Mb: x16, x32 2.5V VEXT, 1.8V VDD, 1.8V VDDQ, RLDRAM
Electrical Characteristics
Electrical Characteristics
Stresses greater than those listed may cause permanent damage to the device. This is a
stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may
affect reliability.
Figure 30:
Absolute Maximum Ratings
Parameter
Min
Storage temperature
I/O voltage
Voltage on VEXT supply relative to VSS
Voltage on VDD supply relative to VSS
Voltage on VDDQ supply relative to VSS
Junction temperature
-55
-0.3V
-0.3
-0.3
-0.3
Max
Units
Notes
°C
V
V
V
V
°C
1
+150
VDDQ + 0.3
+2.8
+2.1
+2.1
110
Notes: 1. Junction temperature depends upon package type, cycle time, loading, ambient temperature, and airflow.
Recommended DC Operation Ranges
All values are recommended operating conditions unless otherwise noted. External on
board (PCB) capacitance values are required as follows:
•
•
•
•
Table 19:
VDDQ: 2 × 0.1µF/device
VDD: 2 × 0.1µF/device
VREF: 0.1µF/device
VEXT : 0.1µF/device
DC Electrical Characteristics and Operating Conditions
0°C ≤ TC ≤ +95°C; +1.7V ≤ VDD ≤ +1.95V unless otherwise noted
Descriptions
Supply voltage
Supply voltage
Isolated output buffer supply
Reference voltage
Symbol
Min
Max
Units
Notes
VEXT
VDD
VDDQ
VREF
2.38
1.7
1.7
0.49 × VDDQ
2.63
1.95
VDD
0.51 × VDDQ
V
V
V
V
1
1
1, 2
1, 3, 4
Notes: 1. All voltages referenced to VSS (GND).
2. During normal operation, VDDQ must not exceed VDD.
3. Typically the value of VREF is expected to be 0.5x VDDQ of the transmitting device. VREF is
expected to track variations in VDDQ.
4. Peak to peak AC noise on VREF must not exceed 2% VREF(DC).
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256Mbx16x32RLDRAM_2.fm - Rev F 8/05 EN
35
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001 Micron Technology, Inc. All rights reserved.
256Mb: x16, x32 2.5V VEXT, 1.8V VDD, 1.8V VDDQ, RLDRAM
Recommended DC Operation Ranges
Table 20:
DC Electrical Characteristics and Operating Conditions
0°C ≤ TC ≤ +95°C; +1.7V ≤ VDD ≤ +1.95V unless otherwise noted
Description
Input high (Logic 1) voltage
Input low (Logic 0) voltage
Output high voltage
Output low voltage
Input high (Logic 1) voltage
Input low (Logic 0) voltage
Output high voltage
Output low voltage
Conditions
Symbol
Matched impedance mode
Matched impedance mode
Matched impedance mode
Matched impedance mode
HSTL strong
HSTL strong
HSTL strong
HSTL strong
VIH
VIL
VOH
VOL
VIH
VIL
VOH
VOL
ILC
ILI
ILO
IREF
Clock input leakage current
Input Leakage current
Output leakage current
Reference voltage current
0V ≤ VIN ≤ VDDQ
MIn
Max
VREF + 0.15 VDDQ + 0.3
VSSQ - 0.3 VREF - 0.15
VDDQ
0
VREF + 0.1 VDDQ + 0.3
VSSQ - 0.3
VREF - 0.1
VDDQ - 0.4
0.4
-5
5
-5
5
-5
5
-5
5
Units
Notes
V
V
V
V
V
V
V
V
µA
µA
µA
µA
1, 2
1, 2
1, 3, 4
1, 3, 4
1, 2
1, 2
1, 3, 4
1, 3, 4
Notes: 1. All voltages referenced to VSS (GND).
2. Overshoot: VIH(AC) ≤ VDD + 0.7V for t ≤ tCK/2
Undershoot: VIL(AC) ≥ −0.5V for t ≤ tCK/2
During normal operation, VDDQ must not exceed VDD. Control input signals may not
have pulse widths less than tCK/2 or operate at frequencies exceeding tCK (MAX).
3. AC load current is higher than the shown DC values. AC I/O curves are available upon
request.
4. HSTL outputs meet JEDEC HSTL Class I and Class II standards.
Table 21:
Capacitance
Description
Address/Control input capacitance
Input/Output capacitance (DQ)
Conditions
Symbol
MIn
Max
Units
TA = 25°C; f = 1 MHz
CI
CO
2.0
2.0
4.0
4.0
pF
pF
CCK
2.0
4.0
pF
Clock capacitance
Table 22:
AC Electrical Characteristics and Operating Conditions
0°C ≤ TC ≤ +95°C; +1.7V ≤ VDD ≤ +1.95V unless otherwise noted
Description
Input high (Logic 1) voltage
Input low (Logic 0) voltage
Input high (Logic 1) voltage
Input low (Logic 0) voltage
Figure 31:
Conditions
Symbol
MIn
Max
Units
Matched impedance mode
Matched impedance mode
HSTL strong
HSTL strong
VIH
VIL
VIH
VIL
VREF + 0.3
VSSQ - 0.3
VREF + 0.2
VSSQ - 0.3
VDDQ + 0.3
VREF - 0.3
VDDQ + 0.3
VREF - 0.2
V
V
V
V
Output Test Conditions
VDDQ/2
50 Ohm
DQ
Test point
10 pF
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256Mbx16x32RLDRAM_2.fm - Rev F 8/05 EN
36
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001 Micron Technology, Inc. All rights reserved.
256Mb: x16, x32 2.5V VEXT, 1.8V VDD, 1.8V VDDQ, RLDRAM
Recommended DC Operation Ranges
Table 23:
IDD Operating Conditions and Maximum Limits
+0°C ≤ TC ≤ +95°C; VDD = MAX unless otherwise noted
Max
Description
Standby current
Active standby
current
Incremental
current
Incremental
current
Burst refresh
current
Distributed
refresh current
Operating supply
current example
Operating supply
current example
Conditions
Symbol
t
CK = Idle
All banks idle, no inputs toggling
ISB1 (VDD) X32
ISB1 (VDD) X16
ISB1 (VEXT)
t
CK = MIN, CS# = 1
ISB2 (VDD) X32
No commands, half address/data toggle ISB2 (VDD) X16
up to once every 4 clock cycles
ISB2 (VEXT)
BL = 2, tCK = MIN, tRC = MIN,
IDD1 (VDD) X32
1 bank active, half address data toggles IDD1 (VDD) X16
once per tRC, read followed by write
IDD1 (VEXT)
sequence
BL = 4, tCK = MIN, tRC = MIN,
IDD2 (VDD) X32
1 bank active, half address/data toggle IDD2 (VDD) X16
once per tRC, read followed by write
IDD2 (VEXT)
sequence
tCK = MIN, tRC = MIN
IREF1 (VDD) X32
Cyclic bank refresh, data inputs are
IREF1 (VDD) X16
switching
IREF1 (VEXT)
tCK = MIN, tRC = MIN
IREF2 (VDD) X32
Single bank refresh, half address/data
IREF2 (VDD) X16
toggle
IREF2 (VEXT)
IDD2W(VDD) X32
BL = 2, tCK = MIN, 8 bank cyclic access,
half of address bits change every 4 clock IDD2W (VDD) X16
cycles, continuous data
IDD2W(VEXT)
IDD4W (VDD) X32
BL = 4, tCK = MIN, 8 bank cyclic access,
half of address bits change every 2
IDD4W (VDD) X16
clocks, continuous data
IDD4W (VEXT)
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256Mbx16x32RLDRAM_2.fm - Rev F 8/05 EN
37
-33
-4
-5
Units
59
55
12
280
255
12
287
263
16
59
55
12
271
244
12
266
243
16
59
55
12
228
205
12
240
221
16
mA
341
285
20
326
273
20
300
250
20
mA
460
451
79
282
265
20
807
713
46
723
549
46
431
419
68
268
254
20
706
616
40
634
476
40
357
347
57
249
231
20
598
519
34
521
392
34
mA
mA
mA
mA
mA
mA
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001 Micron Technology, Inc. All rights reserved.
256Mb: x16, x32 2.5V VEXT, 1.8V VDD, 1.8V VDDQ, RLDRAM
Package Dimensions
Package Dimensions
Figure 32:
144-Ball µBGA
10.70 CTR
10º TYP
SEATING PLANE
2.40 CTR
A
0.08 A
144X ∅ 0.45
DIMENSIONS APPLY
TO SOLDER BALLS
POST REFLOW. THE
PRE-REFLOW BALL
DIAMETER IS 0.50 ON
A 0.40 SMD BALL PAD.
0.08 MAX
0.44 ±0.05
0.26 ±0.05
0.39 ±0.05
8.80
0.80 TYP
BALL A12
BALL A1
BALL A1 ID
BALL A1 ID
1.00 TYP
18.50 ±0.10
17.00 15.40
8.50
17.90
CTR
9.25 ±0.05
4.40
MOLD COMPOUND: EPOXY NOVOLAC
SUBSTRATE: PLASTIC LAMINATE
SOLDER BALL MATERIAL:
62% Sn, 36% Pb, 2%Ag OR
96.5% Sn, 3%Ag, 0.5% Cu
5.50 ±0.05
11.00 ±0.10
Note:
All dimensions in millimeters.
®
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900
prodmktg@micron.com www.micron.com Customer Comment Line: 800-932-4992
Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc.
RLDRAM is a trademark of Infineon Technologies AG in various countries, and is used by Micron Technology, Inc. under
license from Infineon. All other trademarks are the property of their respective owners.
This data sheet contains minimum and maximum limits specified over the complete power supply and temperature range
for production devices. Although considered final, these specifications are subject to change, as further product
development and data characterization sometimes occur.
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256Mbx16x32RLDRAM_2.fm - Rev F 8/05 EN
38
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©2001 Micron Technology, Inc. All rights reserved.
